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4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 1 en29f040 rev. d, issue date: 2001/07/05 features 5.0v operation for read/write/erase operations fast read access time - 45ns, 55ns, 70ns, and 90ns sector architecture: - 8 uniform sectors of 64kbytes each - supports full chip erase - individual sector erase supported - sector protection: hardware locking of sectors to prevent program or erase operations within individual sectors high performance program/erase speed - byte program time: 10s typical - sector erase time: 500ms typical - chip erase time: 3.5s typical low standby current - 1a cmos standby current-typical - 1ma ttl standby current low power active current - 30ma active read current - 30ma program/erase current jedec standard program and erase commands jedec standard data polling and toggle bits feature single sector and chip erase sector unprotect mode embedded erase and program algorithms erase suspend / resume modes: read and program another sector during erase suspend mode 0.35 m double-metal double-poly triple-well cmos flash technology low vcc write inhibit < 3.2v 100k endurance cycle package options - 32-pin pdip - 32-pin plcc - 32-pin tsop (type 1) commercial and industrial temperature ranges general description the en29f040 is a 4-megabit, electrically erasable, read/write non-volatile flash memory. organized into 512k words with 8 bits per word, the 4m of memory is arranged in eight uniform sectors of 64kbytes each. any byte can be programmed typically in 10s. the en29f040 features 5.0v voltage read and write operation, with access times as fast as 45ns to eliminate the need for wait states in high-performance microprocessor systems. the en29f040 has separate output enable ( oe ), chip enable ( ce ), and write enable ( we ) controls, which eliminate bus contention issues. this device is designed to allow either single (or multiple) sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. the device can sustain a minimum of 100k program/erase cycles on each sector. en29f040 4 megabit (512k x 8-bit) flash memory
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 2 en29f040 rev. d, issue date: 2001/07/05 table 1. pin description figure 1. logic diagram pin name function a0-a18 addresses dq0-dq7 data inputs/outputs ce chip enable oe output enable we write enable vcc supply voltage (5v 10% ) vss ground table 2. sector architecture sector addresses size (kbytes) a18 a17 a16 7 70000h - 7ffffh 64 1 1 1 6 60000h - 6ffffh 64 1 1 0 5 50000h C 5ffffh 64 1 0 1 4 40000h C 4ffffh 64 1 0 0 3 30000h C 3ffffh 64 0 1 1 2 20000h - 2ffffh 64 0 1 0 1 10000h - 1ffffh 64 0 0 1 0 00000h - 0ffffh 64 0 0 0 en29f040 8 dq0 - dq7 a0 - a18 18 vcc we ce oe vss
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 3 en29f040 rev. d, issue date: 2001/07/05 block diagram we ce oe state control command register erase voltage generator input/output buffers program voltage generator chip enable output enable logic data latch y-decoder x-decoder y-gating cell matrix timer vcc detector a0-a18 vcc vss dq0-dq7 address latch block protect switches stb stb
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 4 en29f040 rev. d, issue date: 2001/07/05 figure 2. pdip figure 3. plcc figure 4. tsop
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 5 en29f040 rev. d, issue date: 2001/07/05 table 3. operating modes 4m flash user mode table ce we oe a9 a8 a6 a5 a1 a0 ax/y dq(0-7) user mode standby h x x x x x x x x x hi-z read l h l a9 a8 a6 a5 a1 a0 ax/y dq (0-7) output disable l h h x x x x x x x hi-z read manufacture id l h l vid l/h l x l l x manufacture id read device id l h l vid l/h l x l h x device id (t/b) verify sector protection l h l vid x l x h l x code sector protection l pulse l vid vid x l x x x x x verify sector unprotection l h l vid x h x h l x code sector unprotection pulse l vid vid l x x h x x x x write l l h a9 a8 a6 a5 a1 a0 ax/y din (0-7) notes: 1) l = v il , h = v ih , v id = 11.0v 0.5v 2) x = dont care, either v ih or v il 3) ax/y: ax = addr(x), ay = addr(y) table 4. device identifiction 4m flash manufacturer/device id table a8 a6 a1 a0 dq(7-0) hex read manufacturer id h (1) l l l manufacturer id 1c read device id h (2) l l h device id 04 notes: 1) if a manufacturing id is read with a8 = l, the chip will output a configuration code 7fh. a further manufacturing id must be read with a8 = h. 2) if a device id is read with a8 = l, the chip will output a configuration code 7fh. a further device id must be read with a8 = h.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 6 en29f040 rev. d, issue date: 2001/07/05 user mode definitions standby mode the en29f040 has a cmos-compatible standby mode, which reduces the current to < 1a (typical). it is placed in cmos-compatible standby when the ce pin is at v cc 0.5. the device also has a ttl-compatible standby mode, which reduces the maximum v cc current to < 1ma. it is placed in ttl-compatible standby when the ce pin is at v ih . when in standby modes, the outputs are in a high-impedance state independent of the oe input. read mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see reset command section. see also requirements for reading array data in the device bus operations section for more information. the read operations table provides the read parameters, and read operation timings diagram shows the timing diagram. output disable mode when the oe pin is at a logic high level (v ih ), the output from the en29f040 is disabled. the output pins are placed in a high impedance state. auto select identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7Cdq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (10.5 v to 11.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are dont care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7Cdq0. to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see command definitions for details on using the autoselect mode.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 7 en29f040 rev. d, issue date: 2001/07/05 reset command writing the reset command to the device resets the device to reading array data. address bits are dont care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). write mode programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 5 (command definitions) shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see write operation status for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set dq5 to 1, or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1. command definitions the operations of the en29f040 are selected by one or more commands written into the command register to perform read/reset memory, read id, read sector protection, program, sector erase, chip erase, erase suspend and erase resume. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command table (table 5). incorrect addresses, incorrect data values or improper sequences will reset the device to the read mode.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 8 en29f040 rev. d, issue date: 2001/07/05 table 5. en29f040 command definitions 1 st write cycle 2 nd write cycle 3 rd write cycle 4 th write cycle 5 th write cycle 6 th write cycle command sequence read/reset write cycles reqd addr data addr data addr data addr data addr data addr data read 1 ra rd reset 1 xxxh f0h read/reset 4 555h aah 2aah 55h 555h f0h ra rd autoselect manufacturer id 4 555h aah 2aah 55h 555h 90h 000h/ 100h 7fh/ 1ch autoselect device id 4 555h aah 2aah 55h 555h 90h 001h/ 101h 7fh/ 04h autoselect sector protect verify 4 555h aah 2aah 55h 555h 90h ba & 02h 00h/ 01h byte program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h notes: ra = read address: address of the memory location to be read. this one is a read cycle. rd = read data: data read from location ra during read operation. this one is a read cycle. pa = program address: address of the memory location to be programmed pd = program data: data to be programmed at location pa ba = sector address: address of the sector to be erased. address bits a17-a13 uniquely select any sector. byte programming command programming the en29f040 is performed on a byte-by-byte basis using a four bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automatically. address is latched on the falling edge of ce or we , whichever is last; data is latched on the rising edge of ce or we , whichever is first. the program operation is completed when en29f040 returns the equivalent data to the programmed location. programming status may be checked by sampling data on dq7 ( data polling) or on dq6 (toggle bit). changing data from 0 to 1 requires an erase operation. when programming time limit is exceeded, dq5 will produce a logical 1 and a reset command can return the device to read mode. chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 9 en29f040 rev. d, issue date: 2001/07/05 any commands written to the chip during the embedded erase algorithm are ignored. t he system can determine the status of the erase operation by using dq7, dq6, or dq2. see write operation status for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. flowchart 4 illustrates the algorithm for the erase operation. see the erase/program operations tables in ac characteristics for parameters, and chip/sector erase operation timings for timing waveforms. sector erase command sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. this device does not support multiple sector erase commands. sector erase operation will commence immediately after the first 30h command is written. the first sector erase operation must finish before another sector erase command can be given. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to write operation status for information on these status bits. flowchart 4 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend / resume command the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are dont-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase- suspended sectors produces status data on dq7Cdq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 10 en29f040 rev. d, issue date: 2001/07/05 the system must write the erase resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/unprotection must be implemented using programming equipment. the procedure re- quires a high voltage (v id ) on address pin a9 and the control pins. contact eon silicon devices, inc. for an additional supplement on this feature.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 11 en29f040 rev. d, issue date: 2001/07/05 write operation status dq7 dat a polling the en29f040 provides data polling on dq7 to indicate to the host system the status of the embedded operations. the data polling feature is active during the byte programming, sector erase, chip erase, and erase suspend. (see table 6) when the byte programming is in progress, an attempt to read the device will produce the complement of the data last written to dq7. upon the completion of the byte programming, an attempt to read the device will produce the true data last written to dq7. for the byte programming, data polling is valid after the rising edge of the fourth we or ce pulse in the four-cycle sequence. when the embedded erase is in progress, an attempt to read the device will produce a 0 at the dq7 output. upon the completion of the embedded erase, the device will produce the 1 at the dq7 output during the read. for chip erase, the data polling is valid after the rising edge of the sixth we or ce pulse in the six-cycle sequence. for sector erase, data polling is valid after the last rising edge of the sector erase we or ce pulse. data polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. otherwise, data polling may give an inaccurate result if the address used is in a protected sector. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable ( oe ) is low. this means that the device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operations and dq7 has a valid data, the data output on dq0-dq6 may be still invalid. the valid data on dq0-dq7 will be read on the subsequent read attempts. the flowchart for data polling (dq7) is shown on flowchart 5. the data polling (dq7) timing diagram is shown in figure 8. dq6 toggle bit i the en29f040 provides a toggle bit on dq6 to indicate to the host system the status of the embedded programming and erase operations. (see table 6) during an embedded program or erase operation, successive attempts to read data from the device at any address (by toggling oe or ce ) will result in dq6 toggling between zero and one. once the embedded program or erase operation is complete, dq6 will stop toggling and valid data will be read on the next successive attempts. during byte programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four-cycle sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth-cycle sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is also active during the sector erase time-out window.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 12 en29f040 rev. d, issue date: 2001/07/05 in byte programming, if the sector being written to is protected, dq6 will toggles for about 2 m s, then stop toggling without the data in the sector having changed. in sector erase or chip erase, if all selected sectors are protected, dq6 will toggle for about 100 m s. the chip will then return to the read mode without changing data in all protected sectors. toggling either ce or oe will cause dq6 to toggle. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 9 . dq5 exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. ( the toggle bit (dq6) should also be checked at this time to make sure that the dq5 is not a 1 due to the device having returned to read mode.) this is a failure condition that indicates the program or erase cycle was not successfully completed. . data polling (dq7), toggle bit (dq6) and erase toggle bit (dq2) still function under this condition. setting the ce to v ih will partially power down the device under those conditions. the dq5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. dq2 erase toggle bit ii the toggle bit on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 6 to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the section dq2: toggle bit explains the algorithm. see also the dq6: toggle bit i subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7Cdq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 13 en29f040 rev. d, issue date: 2001/07/05 toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of flowchart 6). table 6. status register bits dq name logic level definition 1 erase complete or erase sector in erase suspend 0 erase on-going dq7 program complete or data of non-erase sector during erase suspend 7 data polling dq7 program on-going -1-0-1-0-1-0-1- erase or program on-going dq6 read during erase suspend 6 toggle bit -1-1-1-1-1-1-1- erase complete 1 program or erase error 5 error bit 0 program or erase on-going -1-0-1-0-1-0-1- chip erase, erase or erase suspend on currently addressed sector. (when dq5=1, erase error due to currently addressed sector. program during erase suspend on-going at current address 2 toggle bit dq2 erase suspend read on non erase suspend sector notes: dq7 data polling: indicates the p/e c status check during program or erase, and on completion before checking bits dq5 for program or erase success. dq6 toggle bit: remains at constant level when p/e operations are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5 error bit: set to 1 if failure in programming or erase dq2 toggle bit: indicates the erase status and allows identification of the erased sector.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 14 en29f040 rev. d, issue date: 2001/07/05 data protection power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce = v il , we = v il and oe = v ih , the device will not accept commands on the rising edge of we . low v cc write inhibit during v cc power-up or power-down , the en20f040 locks out write cycles to protect against any unintentional writes. if v cc < v lok , the command register is disabled and all internal program or erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until v cc > v lko. write noise pulse protection noise pulses less than 5ns on oe , ce or we will neither initiate a write cycle nor change the command register. logical inhibit if ce =v ih or we =v ih , writing is inhibited. to initiate a write cycle, ce and we must be a logical zero. if ce , we , and oe are all logical zero (not recommended usage), it will be considered a write. sector protect and unprotect the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operation in previously protected sectors. sector protection/unprotection must be implemented using programming equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. contact eon silicon devices, inc. for an additional supplement on this feature.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 15 en29f040 rev. d, issue date: 2001/07/05 embedded algorithms flowchart 1. embedded program start write program command sequence (shown below) data poll device last address? programming done increment address no yes flowchart 2. embedded program command sequence see the command definitions section for more information. 2aah / 55h 555h / aah 555h / a0h program address / program data
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 16 en29f040 rev. d, issue date: 2001/07/05 flowchart 3. embedded erase start write erase command sequence (shown below) data polling device or toggle bit successfully completed erase done
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 17 en29f040 rev. d, issue date: 2001/07/05 flowchart 4. embedded erase command sequence see the command definitions section for more information. chip erase sector erase 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 555h/aah 2aah/55h 555h/80h 555h/aah 2aah/55h sector address/30h
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 18 en29f040 rev. d, issue date: 2001/07/05 flowchart 5. dat a polling algorithm no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read data start read data fail pass
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 19 en29f040 rev. d, issue date: 2001/07/05 flowchart 6. toggle bit algorithm no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read data start read data fail pass
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 20 en29f040 rev. d, issue date: 2001/07/05 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65c to +125c ambient temperature with power applied. . . . . . . . . . . . . . C55c to +125c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . . . . C0.5 v to 7.0 v a9, oe# (note 2) . . . . . . . . . . . . . . . C0.5 v to 11.5 v all other pins (note 1) . . . . . . . . . . . . C0.5 v to vcc+0.5v output short circuit current (note 3) . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may undershoot v ss to C1.0v for periods of up to 50 ns and to C2.0 v for periods of up to 20 ns. see left figure below. maximum dc voltage on input and i/o pins is v cc + 0.5 v. during voltage transitions, input and i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see right figure below. 2. minimum dc input voltage on a9 pin is C0.5 v. during voltage transitions, a9 and oe# may undershoot v ss to C1.0v for periods of up to 50 ns and to C2.0 v for periods of up to 20 ns. see left figure. maximum dc input voltage on a9 and oe# is 11.5 v which may overshoot to 12.5 v for periods up to 20 ns. 3. no more than one output shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ). . . . . . . . . . -40c to +85c v cc supply voltages v cc for 5% devices . . . . . . . . . . . . +4.75 v to +5.25 v v cc for 10% devices . . . . . . . . . . . +4.50 v to +5.50 v operating ranges define those limits between which the functionality of the device is guaranteed. maximum negative overshoot maximum positive overshoot waveform waveform
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 21 en29f040 rev. d, issue date: 2001/07/05 table 7. dc characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 5.0v 10%) symbol parameter test conditions min max unit i li input leakage current 0v v in vcc 5 a i lo output leakage current 0v v out vcc 5 a i cc1 supply current (read) ttl byte ce = v il ; oe = v ih ; f = 6mhz 30 ma i cc2 supply current (standby) ttl ce = v ih 1.0 ma i cc3 supply current (standby) cmos ce = vcc 0.3v 5.0 a i cc4 supply current (program or erase) byte program, sector or chip erase in progress 30 ma v il input low voltage -0.5 0.8 v v ih input high voltage 2 vcc + 0.5 v v ol output low voltage i ol = 2 ma 0.45 v v oh output high voltage ttl i oh = -2.5 ma 2.4 v output high voltage cmos i oh = -100 a vcc - 0.4v v v id a9 voltage (electronic signature) 10.5 11.5 v i lit a9 current (electronic signature) a9 = v id 100 a v lko supply voltage (erase and program lock-out) 3.2 4.2 v
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 22 en29f040 rev. d, issue date: 2001/07/05 table 8. ac characteristics read-only operations characteristics parameter symbols speed options jedec standard description test setup -45 -55 -70 -90 unit t avav t rc read cycle time min 45 55 70 90 ns t avqv t acc address to output delay ce = v il oe = v il max 45 55 70 90 ns t elqv t ce chip enable to output delay oe = v il max 45 55 70 90 ns t glqv t oe output enable to output delay max 25 30 30 35 ns t ehqz t df chip enable to output high z max 10 15 20 20 ns t ghqz t df output enable to output high z max 10 15 20 20 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min 0 0 0 0 ns notes: for -45, -55 vcc = 5.0v 5% output load : 1 ttl gate and 30pf input rise and fall times: 5ns input rise levels: 0.0 v to 3.0 v timing measurement reference level, input and output: 1.5 v for all others: vcc = 5.0v 10% output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level, input and output: 0.8 v and 2.0 v
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 23 en29f040 rev. d, issue date: 2001/07/05 table 9. ac characteristics write (erase/program) operations parameter symbols speed options jedec standard description -45 -55 -70 -90 unit t avav t wc write cycle time min 45 55 70 90 ns t avwl t as address setup time min 0 0 0 0 ns t wlax t ah address hold time min 35 45 45 45 ns t dvwh t ds data setup time min 20 25 30 45 ns t whdx t dh data hold time min 0 0 0 0 ns t oes output enable setup time min 0 0 0 0 ns read min 0 0 0 0 ns t oeh output enable hold time toggle and data polling min 10 10 10 10 ns t ghwl t ghwl read recovery time before write ( oe high to we low) min 0 0 0 0 ns t elwl t cs ce setuptime min 0 0 0 0 ns t wheh t ch ce hold time min 0 0 0 0 ns t wlwh t wp write pulse width min 25 30 35 45 ns t whdl t wph write pulse width high min 20 20 20 20 ns typ 7 7 7 7 s t whwh1 t whwh1 programming operation max 200 200 200 200 s typ 0.3 0.3 0.3 0.3 s t whwh2 t whwh2 sector erase operation max 5 5 5 5 s typ 3 3 3 3 s t whwh3 t whwh3 chip erase operation max 35 35 35 35 s t vcs vcc setup time min 50 50 50 50 s t vidr rise time to v id min 500 500 500 500 ns
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 24 en29f040 rev. d, issue date: 2001/07/05 table 10. ac characteristics write (erase/program) operations alternate ce controlled writes parameter symbols speed options jedec standard description -45 -55 -70 -90 unit t avav t wc write cycle time min 45 55 70 90 ns t avel t as address setup time min 0 0 0 0 ns t elax t ah address hold time min 35 45 45 45 ns t dveh t ds data setup time min 20 25 30 45 ns t ehdx t dh data hold time min 0 0 0 0 ns t oes output enable setup time min 0 0 0 0 ns read 0 0 0 0 0 ns t oeh output enable hold time toggle and data polling 10 10 10 10 10 ns t ghel t ghel read recovery time before write ( oe high to ce low) min 0 0 0 0 ns t wlel t ws we setuptime min 0 0 0 0 ns t ehwh t wh we hold time min 0 0 0 0 ns t eleh t cp write pulse width min 25 30 35 45 ns t ehel t cph write pulse width high min 20 20 20 20 ns typ 7 7 7 7 s t whwh 1 t whwh1 programming operation max 200 200 200 200 s typ 0.3 0.3 0.3 0.3 s t whwh 2 t whwh2 sector erase operation max 5 5 5 5 s typ 3 3 3 3 s t whwh 3 t whwh3 chip erase operation max 35 35 35 35 s t vcs vcc setup time min 50 50 50 50 s t vidr rise time to v id min 500 500 500 500 ns
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 25 en29f040 rev. d, issue date: 2001/07/05 table 11. erase and programming performance limits parameter typ max unit comments sector erase time 0.3 5 sec chip erase time 3 35 sec excludes 00h programming prior to erasure byte programming time 7 200 s chip programming time 2 5 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles guaranteed table 12. latch up characteristics parameter description min max input voltage with respect to vss on all pins except i/o pins (including a9 and oe ) -1.0 v 12.0 v input voltage with respect to vss on all i/o pins -1.0 v vcc + 1.0 v vcc current -100 ma 100 ma note : these are latch up characteristics and the device should never be put under these conditions. refer to absolute maximum ratings for the actual operating limits. table 13. 32-pin plcc pi n capacitance @ 25c, 1.0mhz parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v in = 0 8 12 pf table 14. 32-pin tsop pin capacitance @ 25c, 1.0mhz parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 26 en29f040 rev. d, issue date: 2001/07/05 table 15. data retention parameter description test conditions min unit 150c 10 years minimum pattern data retention time 125c 20 years
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 27 en29f040 rev. d, issue date: 2001/07/05 switching waveforms figure 5. ac waveforms for read operations figure 6. ac waveforms for chip/sector erase operations notes: 1. sa is the sector address for sector erase.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 28 en29f040 rev. d, issue date: 2001/07/05 switching waveforms (continued) figure 7. program operation timings notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. /dq7 is the output of the complement of the data written to the device. 4. d out is the output of data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 29 en29f040 rev. d, issue date: 2001/07/05 figure 8. ac waveforms for /data polling during embedded algorithm operations notes: * dq 7 = valid data (the device has completed the embedded operation). figure 9. ac waveforms for toggle bit during embedded algorithm operations notes: * dq 6 stops toggling (the device has completed the embedded operation).
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 30 en29f040 rev. d, issue date: 2001/07/05 switching waveforms (continued) figure 10. alternate /ce controlled write operation timings notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. /dq7 is the output of the complement of the data written to the device. 4. d out is the output of data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence.
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 31 en29f040 rev. d, issue date: 2001/07/05 ordering information en29f040 - 45 p i temperature range (blank) = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package p = 32 plastic dip j = 32 plastic plcc t = 32 plastic tsop speed 45 = 45ns 55 = 55ns 70 = 70ns 90 = 90ns base part number en = eon silicon devices 29f = flash, 5v 040 = 512k x 8
4800 great america parkway, suite 202 tel: 408-235-8680 santa clara, ca 95054 fax: 408-235-8685 32 en29f040 rev. d, issue date: 2001/07/05 revisions list a,b: preliminary c (2001.07.03): pg. 13 logical inhibit section now says that if ce , we , and oe are all logical zero (not recommended usage), it will be considered a write. vid is everywhere changed to be v id =11.5 0.5v d (2001.07.05): block changed to sector deleted sector un/protect flow charts (we have a supplement for that) vid is everywhere changed to be v id =11.0 0.5v lacthup >= 200ma line removed from first page chip erase and sector erase command descriptions modified. dq7,dq5,dq3 status polling descriptions modified. table 12 latchup characteristics modified

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